The present invention relates to a ferroelectric non-volatile memory device and, more particularly, to a ferroelectric non-volatile memory device having a ferroelectric capacitor connected to the gate of a MOS (Metal Oxide Semiconductor) or MIS (Metal Insulator Semiconductor) field effect transistor.
Forming a junction between a semiconductor and a ferroelectric is expected to create, depending on the polarization direction of the ferroelectric, a state in which electrons are induced to the semiconductor surface, or a state in which holes are induced. Attempts have already been made to manufacture non-volatile memory devices which hold memory contents even after power-off operation by using a ferroelectric for the gate insulator film of a MOS field effect transistor and making the two states correspond to "0" and "1". However, no practical devices have been realized yet. Devices with this structure are difficult to manufacture because of the following main reason. If a semiconductor and ferroelectric are joined to each other, an interface state is formed to capture electrons and holes. This stops flowing a necessary current through the source-drain path of a field effect transistor.
To solve this problem, an MFIS (M: Metal or Conductor, F: Ferroelectric, I: Insulator, S: Semiconductor) structure and an MFMIS structure are proposed. In the MFIS structure, a dielectric (paraelectric) film such as a silicon dioxid (SiO.sub.2) film that hardly forms any interface state with a semiconductor is inserted between a ferroelectric film and a semiconductor substrate. In the MFMIS structure, a conductive layer is further sandwiched between a ferroelectric film and a dielectric film. However, if the series structure of ferroelectric and dielectric films is used as the gate insulator film of the field effect transistor, new problems arise: (1) the data write-in voltage rises, and (2) the data retention time is shortened. These problems will be explained.
The rise in the write-in voltage will be explained by exemplifying a structure. In this case, the semiconductor substrate is made of Si, the ferroelectric film is made of lead zirconate titanate (PZT: PbZr.sub.1-x Ti.sub.x O.sub.3), and the dielectric film is made of SiO.sub.2. The MFIS structure may be adopted as the structure of the gate electrode, but the MFMIS structure is adopted for these materials in order to prevent mutual diffusion of Pb atoms in the PZT film and Si atoms in the SiO.sub.2 film. The relative dielectric constant of SiO.sub.2 is 3.9. The relative dielectric constant of PZT takes a value ranging from 200 to 600 depending on the composition ratio of Zr and Ti, and is assumed to be 390 for descriptive convenience. In general, the thickness of the SiO.sub.2 film is 1/10 that of the PZT film.
Since the capacitance of the capacitor is proportional to the relative dielectric constant and inversely proportional to the film, the ferroelectric capacitor and the dielectric capacitor have a capacitance ratio of 10:1. When two capacitors are series-connected, and a voltage is applied to them, the voltage applied to each capacitor is inversely proportional to the capacitance of the capacitor. The voltage applied to the ferroelectric capacitor is 1/10 that to the dielectric capacitor, i.e., 1/11 the total voltage. Assume that an MFS structure in which the PZT film is directly deposited on the Si substrate is formed, and the polarization of the film can be inverted at 5V. An MFMIS structure formed at the same film thickness requires a high voltage of 55V for polarization inversion.
The short data retention time will be explained with reference to FIGS. 9A and 9B. The equivalent circuit of the MFMIS structure is shown in FIG. 9A. In FIG. 9A, reference symbol C.sub.F denotes a ferroelectric capacitor; C.sub.I, a dielectric capacitor. In this case, the whole semiconductor is kept at the ground potential without considering the capacitance of the depletion layer of the semiconductor.
If a voltage V is applied to an upper electrode, voltages V.sub.F and V.sub.I are applied to the two capacitors. The voltages V.sub.F and V.sub.I satisfy EQU V.sub.F +V.sub.I =V (1)
Let .+-.Q be the amount of electric charges appearing in the upper and lower electrodes of the ferroelectric capacitor. As shown in FIG. 9A, the amount .+-.Q of electric charges also appears in the upper and lower electrodes of the dielectric capacitor on a condition that the net electric charges of an intermediate portion between the two capacitors must be 0. Since the dielectric capacitor has the relation of Q=C.sub.I V.sub.I, a substitution of this relation into equation (1) yields: EQU Q=C.sub.I (V-V.sub.F) (2)
The relationship between Q and V.sub.F of the ferroelectric capacitor exhibits hysteresis, as shown in FIG. 9B. This relation given by equation (2) is overlapped in FIG. 9B to obtain a straight line in FIG. 9B. An intersection between the lines represents a voltage applied to the ferroelectric and the amount of electric charges appearing in the capacitor electrode. A point A in FIG. 9B represents Q and V.sub.F when the voltage is kept at V after a large voltage is positively applied, and a point B represents Q and V.sub.F when the voltage is kept at V after a large voltage is negatively applied.
If the voltage is reset to 0 after a large voltage is positively applied, Q and V.sub.F of the ferroelectric capacitor change to a point C in FIG. 9B, and the polarization direction and electric field direction are opposite. In other words, if the gate voltage is reset to 0 to hold data after data is written by applying a positive voltage to the gate electrode of a field effect transistor having the MFIS or MFMIS gate structure, an electric field opposite to the polarization direction is applied to the ferroelectric, and the remanent polarization disappears within a short time. Particularly when the capacitance of the series-inserted dielectric capacitor is small, the magnitude of an inverse electric field comes close to the coercive electric field (electric field necessary for resetting the polarization to 0) of the ferroelectric, and the polarization retention time becomes very short.
The short retention time may not be ignored not only in the MFIS and MFMIS structures but also in the MFS structure. Even if an interface with low trapping state density can be formed between a ferroelectric film and a semiconductor film, and a field effect transistor having a fine MFS gate structure can be manufactured, the ferroelectric capacitor and the capacitance of a depletion layer formed in the semiconductor surface form a series capacitor to pose almost the same problem as shown in FIG. 9B.
For this reason, a conventional non-volatile memory device using a ferroelectric for the gate insulator film of a MOS field effect transistor must adopt the MFIS or MFMIS structure so as not to form an interface state between a semiconductor substrate and the ferroelectric film. However, this type of structure increases the data write-in voltage and shortens the data retention time.